1. Field of the Invention
The present invention is related to programmable switches for integrated circuits, such as configurable system-on-chip circuits, field programmable gate arrays and other devices using programmable switches for interconnecting circuit elements.
2. Description of Related Art
Programmable switches are used in a wide variety circuit devices in order to increase the flexibility of designs. For example, a field programmable gate array includes an array of logic elements and wiring interconnections with thousands of programmable interconnects which are implemented using switches that are programmable in the field. Each programmable switch can connect or disconnect circuit elements, such as nodes in two logic circuits and such as wiring interconnections between modules in the circuit.
In addition to field programmable gate array devices, programmable switches and other programmable logic are being applied for so-called system-on-chip designs, which typically include a processor module, a non volatile memory module, and a programmable logic module among other components. The programmable switches may be used for interconnect structures inside such circuit modules, or between such circuit modules.
It has been proposed to use charge programmable non-volatile memory elements for programmable switches. See U.S. Pat. No. 5,247,478, U.S. Pat. No. 5,764,096 and U.S. Pat. No. 6,122,209. In these patents, floating gate memory cells are used in combination with complex circuitry for programming and erasing such cells. The source and drain of the floating gate memory cell in such switches are coupled to the nodes to be connected or disconnected. The floating gate which controls the operation of the switch is then coupled to independent lines that are used for injecting for removing charge to set the state of the switch. These prior art approaches are relatively large and complex for use as programmable switches in high density integrated circuit environments.
As the uses of programmable switches are expanding, and the density and complexity of the integrated circuits using such switches increases, it is important that the area and the complexity of such switches is reduced. Furthermore, it is desirable that such switches are able to interconnect the circuit elements without significant degradation in voltage across the switch.
The present invention provides a one transistor, non-volatile programmable switch is less complex and requires less area than prior art devices. The programmable switch according to the present invention is used in an integrated circuit, and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A single, non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, gate coupled to an energizing conductor, and a data storage structure constitute the programmable switch.
In one embodiment, the non-volatile programmable transistor consists of a mask programmable ROM cell, in which the data storage structure comprises an implant between the source and drain of the device. In another embodiment, the non-volatile programmable transistor is a charge programmable device, in which the data storage structure comprises the floating gate. In another embodiment, the non-volatile programmable transistor is a charge programmable device (e.g. SONOS cell as described below), in which the data storage structure comprises a nitride layer, or other charge trapping layer, between oxides or other insulators.
In one embodiment, a charge pump is coupled to the energizing conductor to produce a boosted voltage during logical operation of integrated circuit. The boosted voltage in one preferred embodiment comprises a voltage greater than the power potential on said circuit elements by at least a threshold voltage of the programmable transistor, so that voltage dissipation across the programmable switch is minimized or eliminated.
In yet another embodiment, in which the non-volatile programmable transistor is a charge programmable device, programmable circuitry is coupled to the first and second nodes, and to the energizing conductor to apply voltages sufficient to inject and remove charge from the charge storage structure for programming the charge programmable device. The programming circuitry comprises in various embodiments resources inducing Fowler-Nordheim tunneling to remove charge from the charge storage element, resources inducing Fowler-Nordheim tunneling to inject charge into the charge storage element, and resources inducing hot electron injection tunneling to inject charge into the charge storage element, according to needs of the particular implementation.
For integrated circuits in which voltages used for programming and erasing the non-volatile charge programmable device are high relative to the design rule for the circuit elements to be interconnected, a structure coupled with the circuit elements to withstand the high voltages is included. In one embodiment, the circuit element coupled with the first node comprises a transistor, and the structure to withstand the high voltages applied by the programming circuitry comprises a gate insulator adapted to withstand the voltages. In one embodiment, the gate insulator comprises essentially silicon dioxide having a thickness sufficient to withstand the voltages.
In one embodiment, the programming circuitry includes logic to disconnect power from at least one of the circuit element coupled to the first node and the circuit element coupled to the second node while applying energy to inject or remove charged from the charge storage element. Another embodiment, the programming circuitry includes a first voltage conductor coupled to the first node, a second voltage conductor to the second node, and logic to disconnect the first and second voltage conductors from the first and second nodes during logical operation of the integrated circuit.
According to yet other embodiments, the present invention comprises an integrated circuit that includes an array of non-volatile charge programmable memory cells and configurable logic in communication with such array. A plurality of programmable switches is included on integrated circuit for support of the configurable logic as described above. In one embodiment, the programmable switches consist of non-volatile charge programmable devices which have essentially the same cell structure as the non-volatile charge programmable memory cells in the array.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.